FIG. 1 shows a typical example of an existing jitter generation system 10. A jitter controller 11 is coupled to a frequency control input of a controllable oscillator 12 which provides a clock output depending on the input control signal. For example, the clock may be a voltage-controlled oscillator (VCO) which provides a clock signal at a frequency depending on an input voltage that depends on the jitter control. The result is that the clock output is phase or frequency modulated by the jitter control signal provided by the jitter control. The clock output is connected to the clock input of a test signal generator 13. Then the jitter generation system produces a test signal such as a sine wave or square wave with a frequency that deviates slightly with time depending on the voltage signal from the jitter generator.
Those skilled in the art are referred to U.S. Pat. Nos. 3,558,933 to Meyer, 4,797,586 to Traa, 5,175,454 to Murakami, 5,534,808 to Takaki, 5,572,159 to McFarland, and 5,777,501 to AbouSeido. These patents are related to digital delay lines.
The above citations are hereby incorporated herein in whole by reference.